1. Field of the Invention
Embodiments of the present invention relate to methods of passivation layer deposition and, more particularly to methods of passivation layer formation using cyclical deposition techniques for active matrix liquid crystal display applications.
2. Description of the Background Art
Active matrix liquid crystal displays have eliminated many problems associated with passive displays. For example, the fabrication of Active matrix liquid crystal displays have enabled display screens to achieve greater brightness, enhanced readability, a greater variety of color shades, and broader viewing angles compared to displays that employ other technologies. Active matrix liquid crystal displays have therefore become the display technology of choice for numerous applications including computer monitors, television screens, camera displays, avionics displays, as well as numerous other applications.
Active matrix liquid crystal displays generally comprise an array of picture elements called pixels. An electronic switch is associated with each pixel in the display to control the operation thereof. Various electronic switches such as, for example, thin film transistors and organic light emitting diodes (OLED), among others have been investigated to control pixel operation. Thin film transistors, in particular, offer a high degree of design flexibility and device performance.
Thin film transistors are generally formed on large area substrates having a high degree of optical transparency such as, for example, glass. FIG. 1 depicts a cross-sectional schematic view of a thin film transistor (TFT) 22 being a type that has a bottom gate structure. The thin film transistor 22 includes a glass substrate 1 having an underlayer 2 formed on the surface thereof. A gate is formed on the underlayer 2. The gate comprises a gate metal layer 4 and a gate dielectric layer 8. The gate controls the movement of charge carriers in the transistor. A gate dielectric layer 8 formed over the gate metal layer 4 electrically isolates the gate from semiconductor layers 10, 14a, 14b, formed thereon, each of which may function to provide charge carriers to the transistor. A source region 18a of the transistor is formed on semiconductor layer 14a and a drain region 18b of the transistor is formed on semiconductor layer 14b. Finally, a passivation layer 20 encapsulates the thin film transistor 22 to protect it from environmental hazards such as moisture and oxygen.
The passivation layer 20 generally comprises a dielectric material, deposited using conventional techniques, such as, for example, plasma assisted chemical vapor deposition (PECVD). Unfortunately, it is difficult to deposit passivation layers that are continuous (e.g., without gaps or voids) using PECVD techniques. Furthermore, many conventional plasma assisted chemical vapor deposition (PECVD) techniques used to form passivation layers tend to be high temperature processes. High deposition temperatures may not be compatible with the glass substrates upon which the thin film transistors are formed, since the glass may soften and become dimensionally unstable.
Therefore, a need exists to develop a method of forming passivation layers for use in thin film transistors.